1. Field of the Invention
The present invention relates to a process for preparing an SOI semiconductor substrate by bonding and a semiconductor substrate obtained by the process.
2. Related Background Art
Formation of a monocrystalline Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique and has been extensively studied because devices based on utilization of the SOI technique have many advantages that have not been obtained in case of bulk Si substrates for preparing ordinary Si integrated circuits, That is, the following advantages can be obtained by utilizing the SOI technique:
1. Easy dielectric isolation with a possibility of higher level integration PA1 2. Distinguished resistance to radiation PA1 3. Reduced floating capacity with a possibility of higher speed PA1 4. Omission of well formation step PA1 5. Prevention of latch-up PA1 6. Possibility to form a fully depleted field effect transistor by thin film formation, etc.
To obtain the above-mentioned many advantages of device characteristics, processes for forming the SOI structure have been studied for these several ten years. The results are summarized, for example, in the following literature: Special Issue: "Single-crystal silicon on non-single crystal insulators", edited by G. W. Cullen, Journal of Crystal Growth, Volume 63, No. 3, pp. 429-590 (1983).
One of the SOI techniques, which have been now regarded as most promising, is a so called "bonding SOI" technique, which comprises tightly bonding two wafers, at least one of which has an insulating film formed on the surface by oxidation, etc., to each other at their mirror surfaces, applying thereto a heat treatment, thereby reinforcing the bonding at the tightly bonding interface, and grinding or etching the wafer (substrate) from one side thereof, thereby leaving a silicon monocrystalline thin film having a desired thickness to remain on the insulating film. The thin film obtained by the bonding SOI is originally a monocrystalline substrate itself and thus has a good controllability of crystal orientation and very less crystal defects. That is, the bonding SOI has been regarded as most distinguished in the crystal completeness among many SOI techniques.
However, the bonding SOI technique still has problem to be solved. The most important problem is a controllability of film thickness in the step of making one of two bonded silicon substrates into a uniformly thin film. That is, a silicon substrate usually having a thickness of a few hundred .mu.m must be ground or etched to a thickness of a few .mu.m or less than 1 .mu.m, and it is technically difficult to obtain its good controllability and uniformity. Distribution of film thickness is a factor in fluctuations of electric characteristics of device to be formed thereon, and thus these problems must be urgently solved.
Another important problem is suppression of unbonded regions (which will be hereinafter referred to as "voids") generated at the tightly bonding interface between two substrates. Voids are generated by fine dusts having sizes of a few .mu.m or less deposited on the interface on one hand, and it has been reported that the voids are also generated by bubbles introduced merely at the bonding or by water vapor resulting from chemical reactions at the interface when the bonded substrates are heat treated or by contamination of hydrocarbons physically adsorbed on the substrate surfaces before the bonding on the other hand. The size of the voids generated due to these causes is 1 .mu.m or less to a few cm in diameter. When voids are generated in the bonded state of two substrates, the thin film parts on the void regions are peeled away and the void regions turn to holes in a thin film when ground or etched to make the thin film. On the thin film-peeled regions, i.e. holes, no such SOI device can be formed. Even if a thin film remains on the void regions, there is a very high possibility that the thin film parts on the void regions will be peeled away by a device-forming process.
Complete solution of these problems has been found yet, and thus the bonding SOI process has not been commercially employed, though it can provide a monocrystalline thin film of best quality among the SOI techniques.
From the viewpoint of film thickness controllability, the SOI formation based on selective polishing, reported by Hashimoto et al. is known as a process capable of controlling the film thickness with considerably high precision (Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo, 1989, pp. 89-92). The process comprises forming island-shaped regions on the surface of a monocrystalline silicon substrate to serve as an active layer by anisotropic etching or by ordinary mass etching in advance, then oxidizing the surface, forming a deposit of polycrystalline silicon, etc. on the oxide film, flattening the surface of the deposit, bonding the flattened surface to another substrate to serve as a support substrate, grinding or polishing the open side (back side) of the initial monocrystalline silicon substrate. Since the island-shaped regions are formed on the silicon substrate and further oxidized, the oxide film in the region corresponding to the "valley" of the island-shaped regions is exposed at first by the polishing from the back side, and when the polishing is selectively discontinued at the time of the exposure, the island-shaped monocrystalline silicon thin film regions surrounded by the oxide film can be formed. This process based on the selective polishing technique can control the film thickness all over the entire surface of the substrate to some extent, but according to this process the silicon substrate surface is initially separated into island regions, and the thickness, region, etc. of SOI are determined by the area of the island-shaped regions and the depth of the separation groove, and thus the region for SOI (or device) is limited on the substrate. In other words, there coexist monocrystalline regions for forming a device and insulating regions for isolation on the same substrate surface, which is a factor for inhibiting a higher degree of integration or degree of freedom in the device design. This can be the largest disadvantage of SOI formation based on the selective polishing. That is, the insulating region for isolation must perform two functions, i.e. a stopper for the selective polishing and electrical isolation of a device, in the same insulating layer. In the exact control of the polishing end point, the larger the area of the insulating layer, the better. However, from the viewpoint of electrical isolation of a device, the region for isolation has a such a width as to prevent a current leakage. Actually, there is such a problem of antinomy that the width of the region for isolation cannot be too large due to the requirements for a higher degree of integration of a device.
As reported by Wada et al. as to the selective polishing, the so called "overpolishing", which means that the center part of the intermediate region between isolating layers is much more polished, inevitably occurs (8th International Workshop on Future Electron Devices (Three-dimensional ICs and Nanometer Functional Devices) Mar. 14-16, 1990 in Kochi, Japan, pp. 81-84). Strictly speaking, it is quite difficult to conduct film thickness control in a ultrathin film region having a thickness of 0.1 .mu.m or less. That is, the area for region and the width of the region for isolation are strictly limited by the optimum conditions for the selective polishing.
As to a process for forming an SOI device by the similar device isolation process before the above-mentioned prior art, there are reports by Robert C. Frye (U.S. Pat. No. 4,501,060) and W. G. Easter et al. (Electrochemical Society: Extended Abstract of the 180th Society Meeting, Vol. 91-2, Fall 1991, pp 707). According to the former Frye process, a monocrystalline silicon substrate is subjected to anisotropic etching to form an island-shaped region surrounded by a deep groove, and then the surface is oxidized and then polycrystalline silicon is deposited thereon until the polycrystalline silicon completely fills the grooves. Then, the surface of the polycrystalline silicon layer is flattened by polishing and bonded to a support substrate. Finally, the bonded substrates are polished from the open side of the monocrystalline substrate, and the polishing is discontinued when the monocrystalline region is separated in an island shape while leaving an appropriate film thickness to remain. This process has not any particular concept on the film thickness control of SOI thin film by selective polishing and pays no attention to the thin film formation. In this process, there are the same problems of limitation of regions for isolation, degree of freedom in device design, etc. as in the above-mentioned prior art.
The latter Easter et al. process employs the substantially same process steps as in the Frye process and thus has quite similar problems to those of the former Frye process.
As described above, a technique capable of providing a SOI substrate, which can satisfy the preparation of an electronic device of high performance, with a good productivity has not been attained yet.